[__arm_]vqshlq_m[_s32]
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
---|---|---|---|---|---|
Helium | int32x4_t | [__arm_]vqshlq_m[_s32] | (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) | Shift / Left / Vector saturating shift left | |
Description The register variants shift each element of a vector register by the value specified in a source register. The direction of the shift depends on the sign of the element from the second vector register. The immediate variant shifts each element of a vector register to the left by the immediate value. The vector variant shifts each element of the first vector by a value from the least significant byte of the corresponding element of the second vector and places the results in the destination vector. The unsigned variant produces unsigned results, although the operands are signed. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VQSHLT.S32 Argument Preparation inactive register: Qda register: Qmb register: Qnp register: Rp Architectures MVE |
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