[__arm_]vreinterpretq_s32[_u64]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int32x4_t | [__arm_]vreinterpretq_s32[_u64] | (uint64x2_t a) | Data type conversion / Reinterpret casts | |
Description Bitcast the input vector. Results Qd result This intrinsic compiles to the following instructions: NOP Argument Preparation a register: Qd Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.