SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumint8x16_t[__arm_]vreinterpretq_s8[_f32](float32x4_t a)Data type conversion / Reinterpret casts
Description
Bitcast the input vector.
Results
Qd result
This intrinsic compiles to the following instructions:

NOP

Argument Preparation
a register: Qd
Architectures
MVE