SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumuint64x2_t[__arm_]vreinterpretq_u64[_u8](uint8x16_t a)Data type conversion / Reinterpret casts
Description
Bitcast the input vector.
Results
Qd result
This intrinsic compiles to the following instructions:

NOP

Argument Preparation
a register: Qd
Architectures
MVE