SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumuint8x16_t[__arm_]vreinterpretq_u8[_f16](float16x8_t a)Data type conversion / Reinterpret casts
Description
Bitcast the input vector.
Results
Qd result
This intrinsic compiles to the following instructions:

NOP

Argument Preparation
a register: Qd
Architectures
MVE