[__arm_]vreinterpretq_u8[_f16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint8x16_t | [__arm_]vreinterpretq_u8[_f16] | (float16x8_t a) | Data type conversion / Reinterpret casts | |
Description Bitcast the input vector. Results Qd result This intrinsic compiles to the following instructions: NOP Argument Preparation a register: Qd Architectures MVE | |||||
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