[__arm_]vrev32q_m[_s16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int16x8_t | [__arm_]vrev32q_m[_s16] | (int16x8_t inactive, int16x8_t a, mve_pred16_t p) | Vector manipulation / Reverse elements | |
Description Reverse the order of 8-bit or 16-bit elements within each word of the source vector register and places the result in the destination vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VREV32T.16 Argument Preparation inactive register: Qda register: Qmp register: Rp Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.