[__arm_]vrev64q_m[_f32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | float32x4_t | [__arm_]vrev64q_m[_f32] | (float32x4_t inactive, float32x4_t a, mve_pred16_t p) | Vector manipulation / Reverse elements | |
Description Reverse the order of 8-bit, 16-bit or 32-bit elements within each doubleword of the source vector register and places the result in the destination vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VREV64T.32 Argument Preparation inactive register: Qda register: Qmp register: Rp Architectures MVE | |||||
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