[__arm_]vrhaddq_m[_s8]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int8x16_t | [__arm_]vrhaddq_m[_s8] | (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) | Vector arithmetic / Add / Addition | |
Description Add the value of the elements in the first source vector register to the respective elements in the second source vector register. The result is halved and rounded before being written to the destination vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VRHADDT.S8 Argument Preparation inactive register: Qda register: Qnb register: Qmp register: Rp Architectures MVE | |||||
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