[__arm_]vrshlq_m_n[_s16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int16x8_t | [__arm_]vrshlq_m_n[_s16] | (int16x8_t a, int32_t b, mve_pred16_t p) | Shift / Left / Vector rounding shift left | |
Description The vector variant shifts each element of the first vector by a value from the least significant byte of the corresponding element of the second vector and places the results in the destination vector. The register variants shift each element of a vector register by the value specified in a source register. The direction of the shift depends on the sign of the element from the second vector register. Results Qda result This intrinsic compiles to the following instructions: VMSR VPST VRSHLT.S16 Argument Preparation a register: Qdab register: Rmp register: Rp Architectures MVE | |||||
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