[__arm_]vrshrq[_n_s16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int16x8_t | [__arm_]vrshrq[_n_s16] | (int16x8_t a, const int imm) | Shift / Right / Vector rounding shift right | |
Description The immediate variant shifts each element of a vector register to the right by the immediate value. Results Qd result This intrinsic compiles to the following instructions: VRSHR.S16 Argument Preparation a register: Qmimm minimum: 1; maximum: 16 Architectures MVE | |||||
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