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SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumuint32x4_t[__arm_]vsbciq_m[_u32](uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry_out, mve_pred16_t p)Vector arithmetic / Subtract / Subtraction
Description
Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the 'I' variant. FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.
Results
Qd resultRt *carry_out
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VSBCIT.I32 Qd,Qn,Qm

VMRS Rt,FPSCR_nzcvqc

LSR Rt,#29

AND Rt,#1

Argument Preparation
inactive register: Qda register: Qnb register: Qmcarry_out p register: Rp
Architectures
MVE