[__arm_]vsetq_lane[_u64]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint64x2_t | [__arm_]vsetq_lane[_u64] | (uint64_t a, uint64x2_t b, const int idx) | Vector manipulation / Set vector lane | |
Description There are various instructions to semantically represent this instruction, any instruction or sequence of instructions that returns the a vector that is the same as the input vector with the indicated register lane set to the input value is valid. Results Qd result This intrinsic compiles to the following instructions: VMOV Argument Preparation a register: [Rt1,Rt2]b register: Qdidx minimum: 0; maximum: 1 Architectures MVE | |||||
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