SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumint16x8_t[__arm_]vshlcq_m[_s16](int16x8_t a, uint32_t * b, const int imm, mve_pred16_t p)Shift / Left / Whole vector left shift with carry
Description
Logical shift left by 1-32 bits, with carry across beats, carry in from general-purpose register, and carry out to the same general-purpose register. Permits treating a vector register as a single 128-bit scalar. The carry in is from the lower <imm> bits of the general-purpose register, not the upper bits.
Results
Qda resultRdm *b
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VSHLCT Qda,Rdm,#imm

Argument Preparation
a register: Qdab register: Rdmimm minimum: 1; maximum: 32p register: Rp
Architectures
MVE