[__arm_]vshlltq_m[_n_u16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint32x4_t | [__arm_]vshlltq_m[_n_u16] | (uint32x4_t inactive, uint16x8_t a, const int imm, mve_pred16_t p) | Shift / Left / Vector shift left | |
Description Selects an element of 8 or 16-bits from either the top half (T variant) or bottom half (B variant) of each source element, performs a left shift by an immediate value, performs a signed or unsigned left shift by an immediate value and places the 16 or 32-bit results in the destination vector. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VSHLLTT.U16 Argument Preparation inactive register: Qda register: Qmimm minimum: 1; maximum: 16p register: Rp Architectures MVE | |||||
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