[__arm_]vshrnbq[_n_s16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int8x16_t | [__arm_]vshrnbq[_n_s16] | (int8x16_t a, int16x8_t b, const int imm) | Shift / Right / Vector shift right and narrow | |
Description Performs an element-wise narrowing to half-width, with shift, writing the result to either the top half (T variant) or bottom half (B variant) of the result element. The other half of the destination vector element retains its previous value. Results Qd result This intrinsic compiles to the following instructions: VSHRNB.I16 Argument Preparation a register: Qdb register: Qmimm minimum: 1; maximum: 8 Architectures MVE | |||||
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