[__arm_]vshrntq_m[_n_u32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint16x8_t | [__arm_]vshrntq_m[_n_u32] | (uint16x8_t a, uint32x4_t b, const int imm, mve_pred16_t p) | Shift / Right / Vector shift right and narrow | |
Description Performs an element-wise narrowing to half-width, with shift, writing the result to either the top half (T variant) or bottom half (B variant) of the result element. The other half of the destination vector element retains its previous value. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VSHRNTT.I32 Argument Preparation a register: Qdb register: Qmimm minimum: 1; maximum: 16p register: Rp Architectures MVE | |||||
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