[__arm_]vsliq_m[_n_u8]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint8x16_t | [__arm_]vsliq_m[_n_u8] | (uint8x16_t a, uint8x16_t b, const int imm, mve_pred16_t p) | Shift / Left / Vector shift left and insert | |
Description Takes each element in the operand vector, left shifts them by an immediate value, and inserts the results in the destination vector. Bits shifted out of the left of each element are lost. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VSLIT.8 Argument Preparation a register: Qdb register: Qmimm minimum: 0; maximum: 7p register: Rp Architectures MVE | |||||
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