[__arm_]vst1q_p[_u8]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | void | [__arm_]vst1q_p[_u8] | (uint8_t * base, uint8x16_t value, mve_pred16_t p) | Store / Stride | |
Description Stores vector to memory, alias to vstr intrinsics where the element size of the input vector is the same as the element size being stored to memory. Results void result This intrinsic compiles to the following instructions: VMSR VPST VSTRBT.8 Argument Preparation base register: Rnvalue register: Qdp register: Rp Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.