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SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumvoid[__arm_]vstrwq_scatter_shifted_offset_p[_f32](float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p)Store / Scatter
Description
Store consecutive elements to memory from a vector register. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register.
Results
void result
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VSTRWT.32 Qd,[Rn,Qm,UXTW #2]

Argument Preparation
base register: Rnoffset register: Qmvalue register: Qdp register: Rp
Architectures
MVE