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SIMD ISAReturn TypeNameArgumentsInstruction Group
svesvfloat64_tsvcadd[_f64]_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, uint64_t imm_rotation)Complex arithmetic / Complex addition
Description
Complex add with rotate
Results
Zresult.D|Ztied1.D result
When result and op1 are in the same register, this intrinsic compiles to:

FCADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D, #imm_rotation

When result is in a different register from the inputs, this intrinsic compiles to:

MOVPRFX Zresult, Zop1

FCADD Zresult.D, Pg/M, Zresult.D, Zop2.D, #imm_rotation

Argument Preparation
pg register: Pg.Dop1 register: Zop1.D|Ztied1.Dop2 register: Zop2.D
Architectures
A64

Operation

The arguments and result contain complex values as pairs of real and imaginary components, with the real components in even-indexed elements and the imaginary components in odd-indexed elements.

If r is the index of a real component and i is the index of the corresponding imaginary component, return a vector res in which each active element is given by:

imm_rotation == 90
res[r] = op1[r] - op2[i];
res[i] = op1[i] + op2[r];
imm_rotation == 270
res[r] = op1[r] + op2[i];
res[i] = op1[i] - op2[r];

Take the inactive elements of the result from the corresponding elements of op1.

Exceptions

Active signaling NaNs trigger an IEEE Invalid exception but quiet NaNs do not. The following also trigger an IEEE Invalid exception:

  • adding +∞ and -∞ together
  • subtracting an infinity from itself