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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvabdl_s16(int16x4_t a, int16x4_t b)Vector arithmetic / Absolute / Widening absolute difference
Description
Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SABDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation
a register: Vn.4Hb register: Vm.4H
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) absdiff;

result = if accumulate then V[d] else Zeros();
for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    absdiff = Abs(element1 - element2)<2*esize-1:0>;
    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
V[d] = result;