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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvaddhn_high_s64(int32x2_t r, int64x2_t a, int64x2_t b)Vector arithmetic / Add / Narrowing addition
Description
Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

ADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation
r register: Vd.2Sa register: Vn.2Db register: Vm.2D
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize)   result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;