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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint64x2_tvaddl_high_s32(int32x4_t a, int32x4_t b)Vector arithmetic / Add / Widening addition
Description
Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.
Results
Vd.2D result
This intrinsic compiles to the following instructions:

SADDL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation
a register: Vn.4Sb register: Vm.4S
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;