Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvaddl_high_u16(uint16x8_t a, uint16x8_t b)Vector arithmetic / Add / Widening addition
Description
Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

UADDL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation
a register: Vn.8Hb register: Vm.8H
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;