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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat16x8_tvaddq_f16(float16x8_t a, float16x8_t b)Vector arithmetic / Add / Addition
Description
Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.
Results
Vd.8H result
This intrinsic compiles to the following instructions:

FADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation
a register: Vn.8Hb register: Vm.8H
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR[]);

V[d] = result;