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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint64x2_tvaddq_u64(uint64x2_t a, uint64x2_t b)Vector arithmetic / Add / Addition
Description
Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.2D result
This intrinsic compiles to the following instructions:

ADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation
a register: Vn.2Db register: Vm.2D
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;