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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint16x8_tvaddw_s8(int16x8_t a, int8x8_t b)Vector arithmetic / Add / Widening addition
Description
Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.
Results
Vd.8H result
This intrinsic compiles to the following instructions:

SADDW Vd.8H,Vn.8H,Vm.8B

Argument Preparation
a register: Vn.8Hb register: Vm.8B
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;