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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvaddw_u16(uint32x4_t a, uint16x4_t b)Vector arithmetic / Add / Widening addition
Description
Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

UADDW Vd.4S,Vn.4S,Vm.4H

Argument Preparation
a register: Vn.4Sb register: Vm.4H
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;