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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat32x4_tvcaddq_rot90_f32(float32x4_t a, float32x4_t b)Complex arithmetic / Complex addition
Description
Floating-point Complex Add.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

FCADD Vd.4S,Vn.4S,Vm.4S,#90

Argument Preparation
a register: Vn.4S b register: Vm.4S
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element3;

for e = 0 to (elements DIV 2) -1 
    case rot of 
        when '0'
            element1 = FPNeg(Elem[operand2, e*2+1, esize]); 
            element3 = Elem[operand2, e*2, esize];
        when '1'
            element1 = Elem[operand2, e*2+1, esize]; 
            element3 = FPNeg(Elem[operand2, e*2, esize]);   
    Elem[result, e*2,   esize] = FPAdd(Elem[operand1, e*2, esize], element1, FPCR[]);
    Elem[result, e*2+1, esize] = FPAdd(Elem[operand1, e*2+1, esize], element3, FPCR[]);

V[d] = result;