Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat64x1_tvcvt_n_f64_s64(int64x1_t a, const int n)Data type conversion / Conversions
Description
Signed fixed-point Convert to Floating-point (vector). This instruction converts each element in a vector from fixed-point to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.
Results
Dd result
This intrinsic compiles to the following instructions:

SCVTF Dd,Dn,#n

Argument Preparation
a register: Dnn minimum: 1; maximum: 64
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand  = V[n];

bits(esize) element;
FPCRType fpcr    = FPCR[];
boolean merge    = elements == 1 && IsMerging(fpcr);
bits(128) result = if merge then V[d] else Zeros();

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = FixedToFP(element, fracbits, unsigned, fpcr, rounding);

V[d] = result;