Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint64_tvcvtmd_s64_f64(float64_t a)Data type conversion / Conversions
Description
Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.
Results
Dd result
This intrinsic compiles to the following instructions:

FCVTMS Dd,Dn

Argument Preparation
a register: Dn
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];

bits(esize) element;
FPCRType fpcr    = FPCR[];
boolean merge    = elements == 1 && IsMerging(fpcr);
bits(128) result = if merge then V[d] else Zeros();

for e = 0 to elements-1
    element = Elem[operand, e, esize];
    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, fpcr, rounding);

V[d] = result;