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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat32x4_tvcvtq_low_f32_bf16(bfloat16x8_t a)Data type conversion / Conversions
Description
Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SHLL Vd.4S,Vn.8H,#16

Argument Preparation
a register: Vn.8H
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = Vpart[n, part];
bits(2*datasize) result;
integer element;

for e = 0 to elements-1
    element = Int(Elem[operand, e, esize], unsigned) << shift;
    Elem[result, e, 2*esize] = element<2*esize-1:0>;

V[d] = result;