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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat32_tvcvtxd_f32_f64(float64_t a)Data type conversion / Conversions
Description
Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.
Results
Sd result
This intrinsic compiles to the following instructions:

FCVTXN Sd,Dn

Argument Preparation
a register: Dn
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();

bits(2*datasize) operand = V[n];
FPCRType fpcr    = FPCR[];
boolean merge    = elements == 1 && IsMerging(fpcr);
bits(128) result = if merge then V[d] else Zeros();

for e = 0 to elements-1
    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], fpcr, FPRounding_ODD);

if merge then
    V[d] = result;
else
    Vpart[d, part] = Elem[result, 0, datasize];