vdupq_lane_f16
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Neon | float16x8_t | vdupq_lane_f16 | (float16x4_t vec, const int lane) | Vector manipulation / Set all lanes to the same value | |
Description Set all vector lanes to the same value Results Vd.8H result This intrinsic compiles to the following instructions: DUP Argument Preparation vec register: Vn.4Hlane minimum: 0; maximum: 3 Architectures v7, A32, A64 OperationNo operation information. | |||||
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