vdupq_lane_f64
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Neon | float64x2_t | vdupq_lane_f64 | (float64x1_t vec, const int lane) | Vector manipulation / Set all lanes to the same value | |
Description Set all vector lanes to the same value Results Vd.2D result This intrinsic compiles to the following instructions: DUP Argument Preparation vec register: Vn.1Dlane minimum: 0; maximum: 0 Architectures A64 OperationNo operation information. | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.