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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint8x16_tveorq_s8(int8x16_t a, int8x16_t b)Logical / Exclusive OR
Description
Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.
Results
Vd.16B result
This intrinsic compiles to the following instructions:

EOR Vd.16B,Vn.16B,Vm.16B

Argument Preparation
a register: Vn.16Bb register: Vm.16B
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1;
bits(datasize) operand2;
bits(datasize) operand3;
bits(datasize) operand4 = V[n];

case op of
    when VBitOp_VEOR
        operand1 = V[m];
        operand2 = Zeros();
        operand3 = Ones();
    when VBitOp_VBSL
        operand1 = V[m];
        operand2 = operand1;
        operand3 = V[d];
    when VBitOp_VBIT
        operand1 = V[d];
        operand2 = operand1;
        operand3 = V[m];
    when VBitOp_VBIF
        operand1 = V[d];
        operand2 = operand1;
        operand3 = NOT(V[m]);

V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);