Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat16x8_tvfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c)Vector arithmetic / Multiply / Fused multiply-accumulate
Description
Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.
Results
Vd.8H result
This intrinsic compiles to the following instructions:

FMLA Vd.8H,Vn.8H,Vm.8H

Argument Preparation
a register: Vd.8Hb register: Vn.8Hc register: Vm.8H
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then element1 = FPNeg(element1);
    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR[]);

V[d] = result;