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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat32x2_tvfmlsl_laneq_high_f16(float32x2_t r, float16x4_t a, float16x8_t b, const int lane)Vector arithmetic / Multiply / Fused multiply-accumulate
Description
Floating-point Multiply (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.2S result
This intrinsic compiles to the following instructions:

FMLSL2 Vd.2S,Vn.2H,Vm.H[lane]

Argument Preparation
r register: Vd.2Sa b lane minimum: 0; maximum: 7
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize DIV 2) operand1 = Vpart[n,part];
bits(datasize DIV 2) operand2 = Vpart[m,part];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize DIV 2) element1;
bits(esize DIV 2) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize DIV 2];
    element2 = Elem[operand2, e, esize DIV 2];
    if sub_op then element1 = FPNeg(element1);
    Elem[result,e,esize] = FPMulAddH(Elem[operand3, e, esize], element1, element2, FPCR[]);
V[d] = result;