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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat32x4_tvfmlslq_low_f16(float32x4_t r, float16x8_t a, float16x8_t b)Vector arithmetic / Multiply / Fused multiply-accumulate
Description
Floating-point fused Multiply-Subtract Long from accumulator (vector). This instruction negates the values in the vector of one SIMD&FP register, multiplies these with the corresponding values in another vector, and accumulates the product to the corresponding vector element of the destination SIMD&FP register. The instruction does not round the result of the multiply before the accumulation.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

FMLSL Vd.4S,Vn.4H,Vm.4H

Argument Preparation
r register: Vd.4Sa b
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize DIV 2) operand1 = Vpart[n,part];
bits(datasize DIV 2) operand2 = Vpart[m,part];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize DIV 2) element1;
bits(esize DIV 2) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize DIV 2];
    element2 = Elem[operand2, e, esize DIV 2];
    if sub_op then element1 = FPNeg(element1);
    Elem[result,e,esize] = FPMulAddH(Elem[operand3, e, esize], element1, element2, FPCR[]);
V[d] = result;