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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat64x1_tvfms_f64(float64x1_t a, float64x1_t b, float64x1_t c)Vector arithmetic / Multiply / Fused multiply-accumulate
Description
Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.
Results
Dd result
This intrinsic compiles to the following instructions:

FMSUB Dd,Dn,Dm,Da

Argument Preparation
a register: Dab register: Dnc register: Dm
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();

bits(esize) operanda = V[a];
bits(esize) operand1 = V[n];
bits(esize) operand2 = V[m];

FPCRType fpcr = FPCR[];
boolean merge    = IsMerging(fpcr);
bits(128) result = if merge then V[a] else Zeros();

if opa_neg then operanda = FPNeg(operanda);
if op1_neg then operand1 = FPNeg(operand1);
Elem[result, 0, esize] = FPMulAdd(operanda, operand1, operand2, fpcr);

V[d] = result;