Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonfloat64x2_tvfmsq_laneq_f64(float64x2_t a, float64x2_t b, float64x2_t v, const int lane)Vector arithmetic / Multiply / Fused multiply-accumulate
Description
Floating-point fused Multiply-Subtract from accumulator (by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and subtracts the results from the vector elements of the destination SIMD&FP register.
Results
Vd.2D result
This intrinsic compiles to the following instructions:

FMLS Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation
a register: Vd.2Db register: Vn.2Dv register: Vm.2Dlane minimum: 0; maximum: 1
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then element1 = FPNeg(element1);
    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR[]);

V[d] = result;