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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint64_tvget_lane_s64(int64x1_t v, const int lane)Vector manipulation / Extract one element from vector
Description
Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.
Results
Rd result
This intrinsic compiles to the following instructions:

UMOV Rd,Vn.D[lane]

Argument Preparation
v register: Vn.1Dlane minimum: 0; maximum: 0
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(idxdsize) operand = V[n];

X[d] = ZeroExtend(Elem[operand, index, esize], datasize);