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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint8_tvgetq_lane_s8(int8x16_t v, const int lane)Vector manipulation / Extract one element from vector
Description
Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.
Results
Rd result
This intrinsic compiles to the following instructions:

SMOV Rd,Vn.B[lane]

Argument Preparation
v register: Vn.16Blane minimum: 0; maximum: 15
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(idxdsize) operand = V[n];

X[d] = SignExtend(Elem[operand, index, esize], datasize);