vhsub_s32
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
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Neon | int32x2_t | vhsub_s32 | (int32x2_t a, int32x2_t b) | Vector arithmetic / Subtract / Narrowing subtraction | |
Description Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register. Results Vd.2S result This intrinsic compiles to the following instructions: SHSUB Argument Preparation a register: Vn.2Sb register: Vm.2S Architectures v7, A32, A64 Operation
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