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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvhsubq_s32(int32x4_t a, int32x4_t b)Vector arithmetic / Subtract / Narrowing subtraction
Description
Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SHSUB Vd.4S,Vn.4S,Vm.4S

Argument Preparation
a register: Vn.4Sb register: Vm.4S
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer diff;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    diff = element1 - element2;
    Elem[result, e, esize] = diff<esize:1>;

V[d] = result;