vhsubq_u32
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
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Neon | uint32x4_t | vhsubq_u32 | (uint32x4_t a, uint32x4_t b) | Vector arithmetic / Subtract / Narrowing subtraction | |
Description Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register. Results Vd.4S result This intrinsic compiles to the following instructions: UHSUB Argument Preparation a register: Vn.4Sb register: Vm.4S Architectures v7, A32, A64 Operation
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