Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x2x4_tvld4_lane_u32(uint32_t const * ptr, uint32x2x4_t src, const int lane)Load / Stride
Description
Load multiple 4-element structures to four registers. This instruction loads multiple 4-element structures from memory and writes the result to the four SIMD&FP registers, with de-interleaving.
Results
Vt4.2S result.val[3]Vt3.2S result.val[2]Vt2.2S result.val[1]Vt.2S result.val[0]
This intrinsic compiles to the following instructions:

LD4 {Vt.s - Vt4.s}[lane],[Xn]

Argument Preparation
ptr register: Xnsrc register: Vt4.2Slane minimum: 0; maximum: 1
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();

bits(64) address;
bits(64) offs;
bits(datasize) rval;
integer tt;
constant integer ebytes = esize DIV 8;

if HaveMTE2Ext() then
    SetTagCheckedInstruction(tag_checked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n];

offs = Zeros();
for r = 0 to rpt-1
    for e = 0 to elements-1
        tt = (t + r) MOD 32;
        for s = 0 to selem-1
            rval = V[tt];
            if memop == MemOp_LOAD then
                Elem[rval, e, esize] = Mem[address + offs, ebytes, AccType_VEC];
                V[tt] = rval;
            else // memop == MemOp_STORE
                Mem[address + offs, ebytes, AccType_VEC] = Elem[rval, e, esize];
            offs = offs + ebytes;
            tt = (tt + 1) MOD 32;

if wback then
    if m != 31 then
        offs = X[m];
    if n == 31 then
        SP[] = address + offs;
    else
        X[n] = address + offs;