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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint16x4_tvmla_laneq_u16(uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)Scalar arithmetic / Vector multiply-accumulate by scalar
Description
Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register.
Results
Vd.4H result
This intrinsic compiles to the following instructions:

MLA Vd.4H,Vn.4H,Vm.H[lane]

Argument Preparation
a register: Vd.4Hb register: Vn.4Hv register: Vm.8Hlane minimum: 0; maximum: 7
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1) * UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;