Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x2_tvmla_laneq_u32(uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)Scalar arithmetic / Vector multiply-accumulate by scalar
Description
Multiply-Add to accumulator (vector, by element). This instruction multiplies the vector elements in the first source SIMD&FP register by the specified value in the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register.
Results
Vd.2S result
This intrinsic compiles to the following instructions:

MLA Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation
a register: Vd.2Sb register: Vn.2Sv register: Vm.4Slane minimum: 0; maximum: 3
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1) * UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;