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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint32x4_tvmlsl_high_n_s16(int32x4_t a, int16x8_t b, int16_t c)Scalar arithmetic / Vector multiply-accumulate by scalar and widen
Description
Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

SMLSL2 Vd.4S,Vn.8H,Vm.H[0]

Argument Preparation
a register: Vd.4Sb register: Vn.8Hc register: Vm.H[0]
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize)   operand1 = Vpart[n, part];
bits(datasize)   operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1 * element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;